Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), multi-gigabit transceivers (MGTs), and so forth. Many of these tiles include circuits that are sensitive to variations in the silicon manufacturing process. With the decreasing physical geometries of transistors, resistors, capacitors, and other elements in integrated circuits, these process variations are becoming more difficult to compensate for using traditional design techniques.
Sometimes mask revisions are necessary to adjust circuits for process variations, and sometimes mask revisions are made for other reasons. In either case, mask revisions for a PLD can include changes to the values and/or usage of configuration data bits. Current methods of dealing with such mask revisions often require that a PLD user manually generate different bitstreams for different mask revisions of a PLD.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell. The terms “PLD”, “programmable logic device”, and “programmable integrated circuit” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable Switch fabric that programmably interconnects the hard-coded transistor logic.
As noted above, advanced FPGAs can include several different types of programmable logic blocks in the array. For example, FIG. 1 illustrates an FPGA architecture 100 that includes a large number of different programmable tiles including multi-gigabit transceivers (MGTs 101), configurable logic blocks (CLBs 102), random access memory blocks (BRAMs 103), input/output blocks (IOBs 104), configuration and clocking logic (CONFIG/CLOCKS 105), digital signal processing blocks (DSPs 106), specialized input/output blocks (I/O 107) (e.g., configuration ports and clock ports), and other programmable logic 108 such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (PROC 110).
In some FPGAs, each programmable tile includes a programmable interconnect element (INT 111) having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA. The programmable interconnect element (INT 111) also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top of FIG. 1.
For example, a CLB 102 can include a configurable logic element (CLE 112) that can be programmed to implement user logic plus a single programmable interconnect element (INT 111). A BRAM 103 can include a BRAM logic element (BRL 113) in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as four CLBs, but other numbers (e.g., five) can also be used. A DSP tile 106 can include a DSP logic element (DSPL 114) in addition to an appropriate number of programmable interconnect elements. An IOB 104 can include, for example, two instances of an input/output logic element (IOL 115) in addition to one instance of the programmable interconnect element (INT 111). As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element 115 are manufactured using metal layered above the various illustrated logic blocks, and typically are not confined to the area of the input/output logic element 115.
In the pictured embodiment, a columnar area near the center of the die (shown shaded in FIG. 1) is used for configuration, clock, and other control logic. Horizontal areas 109 extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA.
Some FPGAs utilizing the architecture illustrated in FIG. 1 include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, the processor block PROC 110 shown in FIG. 1 spans several columns of CLBs and BRAMs.
Note that FIG. 1 is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a column, the relative width of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of FIG. 1 are purely exemplary. For example, in an actual FPGA more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB columns varies with the overall size of the FPGA.
FIG. 2 illustrates an exemplary analog circuit including a bias generator 210 and an analog sub-circuit 220 driven by the bias generator. This type of circuit can be included, for example, in the analog logic blocks (IO blocks, MGTs, and so forth) of the FPGA of FIG. 1. In this example, analog sub-circuit 220 is a CML buffer (a current mode logic buffer), but other types of circuitry can also be driven by bias generator 210. CML buffer 220 is a well-known differential circuit typically used for high-speed logic. For example, a differential input signal that includes the two complementary signals IN and IN_B drives CML buffer 220, which produces the two complementary output signals OUT and OUT_B. CML buffer 220 includes resistors 221 and 222 and N-channel transistors 223-225, coupled between power high VDD and ground GND as shown in FIG. 2. NMOS transistor 225 generates the tail current for CML buffer 220, and is driven by a bias voltage Vbias, which is generated by bias generator 210. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The value of bias voltage Vbias determines the current drive and voltage swing of CML buffer 220.
Bias generator 210 includes a P-channel pull-up transistor 201 gated by a reference voltage Vref, and two diode-connected NMOS transistors 202-203, coupled together between power high VDD and ground GND as shown in FIG. 2. Note that transistors 202 and 203 are coupled in parallel. As will be clear to those of skill in the art, the number of pull-down transistors can be less than two, two, or greater than two, and the size of the transistors can also vary, as determined by the circuit requirements of the Vbias node. For example, the Vbias node can drive only one destination (e.g., CML buffer 220, as shown), or can drive many destinations (e.g., many copies of buffer 220). The loading on the node is one of many factors that can affect the size and number of transistors 202-203. Other factors can include, for example, the operating voltage of the circuit. Additionally, the operating characteristics of bias generator 210 are typically affected by the process corner of the die including the circuit.
During the fabrication process for integrated circuits, it is very difficult to ensure complete uniformity for all die. For example, the width of minimum-size metal lines and polysilicon lines may vary from lot to lot, from wafer to wafer, or between dice at different locations on the same wafer. The thickness of some features (e.g., oxide layers) may also vary from lot to lot, from wafer to wafer, or between dice at different locations on the same wafer. Further, when an IC product is manufactured by more than one processing facility, these variations may be more pronounced, and/or may include differences in materials as well as feature size or thickness. These process variations may lead to differences in performance and/or other operating characteristics among various IC die.
Die are typically tested and sorted into different categories based on these characteristics. One common sorting technique is to characterize ICs as either slow, typical, or fast devices. These categories are examples of the different “process corners”. A process corner designation may be applied to an entire device, or to a specific type of structure (e.g., an N-channel transistor, a P-channel transistor, a thick oxide transistor, a low threshold transistor, a polysilicon resistor, and so forth). Thus, an IC die may fall into a single process corner, or more than one process corner.
The process corner(s) of an integrated circuit may seriously affect the performance of analog circuitry such as the bias generator circuit 210 shown in FIG. 2. For example, bias generator circuit 210 may generate a different bias voltage Vbias at the slow corner than at the fast corner of the process. Alternatively or additionally, the amount of capacitance that can be driven by bias generator circuit 210, or the speed of operation of the circuits driven by bias generator circuit 210, may vary unacceptably. These effects can be sufficient to make it very difficult to design a bias circuit 210 that will ensure optimum performance from CML buffer 220 at all process corners, particularly given the smaller feature sizes envisioned for future integrated circuits.
Therefore, it is desirable to provide circuits and methods of compensating for process variations and/or mask revisions in integrated circuits.